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X28C512, X28C513
Data Sheet September 29, 2005 FN8106.1
5V, Byte Alterable EEPROM
The X28C512, X28C513 are 64K x 8 EEPROM, fabricated with Intersil's proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable nonvolatile memories, the X28C512, X28C513 are 5V only devices. The X28C512, X28C513 feature the JEDEC approved pin out for byte wide memories, compatible with industry standard EPROMS. The X28C512, X28C513 support a 128-byte page write operation, effectively providing a 39s/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28C512, X28C513 also feature DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28C512, X28C513 support the software data protection option.
Features
* Access Time: 90ns * Simple Byte and Page Write - Single 5V supply * No external high voltages or VPP control circuits - Self-timed * No erase before write * No complex programming algorithms * No overerase problem * Low Power CMOS - Active: 50mA - Standby: 500A * Software Data Protection - Protects data against system level inadvertent writes * High Speed Page Write Capability * Highly Reliable Direct WriteTM Cell - Endurance: 100,000 write cycles - Data retention: 100 years - Early end of write detection - DATA polling - Toggle bit polling * Two PLCC and LCC Pinouts - X28C512 * X28C010 EPROM pin compatible - X28C513 * Compatible with lower density EEPROMs * Pb-Free Plus Anneal Available (RoHS Compliant)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X28C512, X28C513 Block Diagram
X Buffers Latches and Decoder 512Kbit EEPROM Array
A7-A15
A0-A6
Y Buffers Latches and Decoder
I/O Buffers and Latches
I/O0-I/O7 CE OE WE Data Inputs/Outputs Control Logic and Timing
VCC VSS
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FN8106.1 September 29, 2005
X28C512, X28C513 Ordering Information
PART NUMBER X28C512D X28C512DM X28C512J X28C512P X28C512PI X28C513EM X28C512D-12 X28C512DI-12 X28C512DMB-12 X28C512E-12 X28C512EI-12 X28C512EM-12 X28C512FM-12 X28C512FMB-12 X28C512J-12* X28C512JZ-12 (See Note) X28C512JI-12 X28C512JIZ-12 (See Note) X28C512JM-12 X28C512KM-12 X28C512P-12 X28C512PI-12 X28C512RMB-12 X28C513EM-12 X28C513J-12* X28C513JI-12* X28C513JM-12 X28C512D-15 X28C512DI-15 X28C512DMB-15 X28C512E-15 X28C512EM-15 X28C512EMB-15 X28C512FM-15 X28C512FMB-15 X28C512J-15* X28C512JI-15* X28C512JM-15 X28C512P-15 X28C512PI-15 X28C513EM-15 X28C513EMB-15 X28C512J-15 X28C512JI-15 X28C512JM-15 X28C512P-15 X28C512PI-15 X28C512J-12 X28C512J-12 Z X28C512JI-12 X28C512JI-12 Z X28C512JM-12 X28C512KM-12 X28C512P-12 X28C512PI-12 X28C512RMB-12 X28C513EM-12 X28C513J-12 X28C513JI-12 X28C513JM-12 X28C512D-15 X28C512DI-15 X28C512DMB-15 150 X28C512D-12 X28C512DI-12 X28C512DMB-12 120 X28C512J PART MARKING ACCESS TIME (ns) TEMP RANGE (C) 0 to +70 -55 to +125 0 to +70 0 to +70 -40 to +85 -55 to +125 0 to +70 -40 to +85 Mil-STD-883 0 to +70 -40 to +85 -55 to +125 -55 to +125 Mil-STD-883 0 to +70 0 to +70 -40 to +85 -40 to +85 -55 to +125 -55 to +125 0 to +70 -40 to +85 Mil-STD-883 -55 to +125 0 to +70 -40 to +85 -55 to +125 0 to +70 -40 to +85 Mil-STD-883 0 to +70 -55 to +125 Mil-STD-883 -55 to +125 Mil-STD-883 0 to +70 -40 to +85 -55 to +125 0 to +70 -40 to +85 -55 to +125 Mil-STD-883 PACKAGE 32 Ld CERDIP 32 Ld CERDIP 32 Ld PLCC 32 Ld PDIP 32 Ld PDIP 32 Ld LCC 32 Ld CERDIP 32 Ld CERDIP 32 Ld CERDIP 32 Ld LCC 32 Ld LCC 32 Ld LCC 32 Ld Flat Pack 32 Ld Flat Pack 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC 36 Ld CPGA 32 Ld PDIP 32 Ld PDIP 32 Ld Flat Pack 32 Ld LCC 32 Ld PLCC 32 Ld PLCC 32 Ld PLCC 32 Ld CERDIP 32 Ld CERDIP 32 Ld CERDIP 32 Ld LCC 32 Ld LCC 32 Ld LCC 32 Ld Flat Pack 32 Ld Flat Pack 32 Ld PLCC 32 Ld PLCC 32 Ld PLCC 32 Ld PDIP 32 Ld PDIP 32 Ld LCC 32 Ld LCC
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X28C512, X28C513 Ordering Information (Continued)
PART NUMBER X28C513J-15* X28C513JI-15 X28C513JM-15 X28C512E-20 X28C512EI-20 X28C512EM-20 X28C512FM-20 X28C512FMB-20 X28C512JM-20 X28C512KI-20 X28C512KM-20 X28C513EI-20 X28C513EM-20 X28C513EMB-20 X28C513J-20T1 X28C512E-25 X28C512EI-25 X28C512EM-25 X28C512FMB-25 X28C512JM-25 X28C512KM-25 X28C512KMB-25 X28C513EM-25 X28C513EMB-25 *Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART MARKING X28C513J-15 X28C513JI-15 X28C513JM-15
ACCESS TIME (ns) 150
TEMP RANGE (C) 0 to +70 -40 to +85 -55 to +125
PACKAGE 32 Ld PLCC 32 Ld PLCC 32 Ld PLCC 32 Ld LCC 32 Ld LCC 32 Ld LCC 32 Ld Flat Pack 32 Ld Flat Pack 32 Ld PLCC 36 Ld CPGA 36 Ld CPGA 32 Ld LCC 32 Ld LCC 32 Ld LCC 32 Ld PLCC Tape and Reel 32 Ld LCC 32 Ld LCC 32 Ld LCC 32 Ld Flat Pack 32 Ld PLCC 36 Ld CPGA 36 Ld CPGA 32 Ld LCC 32 Ld LCC
200
0 to +70 -40 to +85 -55 to +125 -55 to +125 Mil-STD-883
X28C512JM-20 X28C512KI-20 X28C512KM-20
-55 to +125 -40 to +85 -55 to +125 -40 to +85 -55 to +125 Mil-STD-883
X28C513J-20 250
0 to +70 0 to +70 -40 to +85 -55 to +125 Mil-STD-883
X28C512JM-25 X28C512KM-25 X28C512KMB-25
-55 to +125 -55 to +125 Mil-STD-883 -55 to +125 Mil-STD-883
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X28C512, X28C513 Pinouts
PLCC/LCC
A15 NC NC VCC WE A12
Plastic DIP CERDIP FLAT Pack SOIC (R)
NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O5 I/O4 I/O3 I/O2 I/O1
4 6 A1 13 A2 12 A4 10 A6 8 A12 5 NC 3 I/O0 15 A0 14 A3 11 A5 9 A7 7 A15 NC 2 NC I/O 2 17
PGA
I/O 5 I/O 3 21 19 I/O 6 22 CE 24 OE 26 A9 28 A13 30 A14 31
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
54 3 2 6 7 8 9 10 11
(Top View)
30 32 31 29 1 28 27 26 X28C512 25 24 23 22
NC A14 A13 A8 A9 A11 OE A10 I/O6 A8 A9 A11 NC OE A10 24 23 22 I/O5
I/O 1 VSS I/O 4 I/O 7 16 18 20 23 A10 25
CE 12 13 15 16 17 18 19 20 I/O7 21 14 I/O1 I/O2 VSS I/O3 I/O4 I/O5 NC I/O3 I/O4
Bottom View
A11 27 A8 29 NC NC 32 NC 33
36 NC 1
34 WE 35
A6 A5 A4 A3 A2 A1 A0 NC I/O0
54 3 2 6 7 8 9 10 11
CE I/O7 12 13 15 16 17 18 19 20 I/O6 21 14 I/O1 I/O2 VSS
Pin Descriptions
Addresses (A0-A15) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28C512, X28C513 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C512, X28C513.
Pin Names
SYMBOL A0-A15 I/O0-I/O7 WE CE OE VCC VSS NC DESCRIPTION Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
5
A12 A14
A7
X28C512
VCC
(Top View)
30 32 31 29 1 28 27 26 X28C513 25
A15 VCC WE A13
FN8106.1 September 29, 2005
X28C512, X28C513 Device Operation
Read
Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
DATA Polling (I/O7)
The X28C512, X28C513 feature DATA polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28C512, X28C513, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data.
Write
Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C512, X28C513 support both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms.
Toggle Bit (I/O6)
The X28C512, X28C513 also provide another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete, the toggling will cease, and the device will be accessible for additional read or write operations.
Page Write Operation
The page write feature of the X28C512, X28C513 allow the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28C512, X28C513, prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A15) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively, the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s.
Write Operation Status Bits
The X28C512, X28C513 provide the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.
I/O DP TB 5 4 3 2 1 0
Reserved Toggle Bit DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
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X28C512, X28C513 DATA Polling I/O7
WE Last Write
CE
OE VIH I/O7 HIGH Z VOL VOH X28C512, X28C513 Ready An An An An
A0-A15
An
An
An
FIGURE 2A. DATA POLLING BUS SEQUENCE
Write Data
DATA Polling can effectively halve the time for writing to the X28C512, X28C513. The timing diagram in Figure 2A illustrates the sequence of events on the bus. The software flow diagram in Figure 2B illustrates one method of implementing the routine.
Writes Complete?
No
Yes
Save Last Data and Address
Read Last Address
IO7 Compare? Yes
No
Ready
FIGURE 2B. DATA POLLING SOFTWARE FLOW
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X28C512, X28C513 The Toggle Bit I/O6
Last WE Write
CE
OE
I/O6
VOH * VOL
HIGH Z * X28C512, X28C513 Ready
* Beginning and ending state of I/O6 will vary.
FIGURE 3A. TOGGLE BIT BUS SEQUENCE
Hardware Data Protection
Last Write
The X28C512, X28C513 provide three hardware features that protect nonvolatile data from inadvertent writes. - Noise Protection--A WE pulse typically less than 10ns will not initiate a write cycle. - Default VCC Sense--All write functions are inhibited when VCC is 3.6V. - Write Inhibit--Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Write cycle timing specifications must be observed concurrently.
Load Accum From Addr N
Compare Accum with Addr N
Software Data Protection
No
Compare Ok? Yes
X28C512 Ready
The X28C512, X28C513 offer a software controlled data protection feature. The X28C512, X28C513 are shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28C512, X28C513 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28C512, X28C513 are also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. Note: The data in the three-byte enable sequence is not written to the memory array.
FIGURE 3B. TOGGLE BIT SOFTWARE FLOW
The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28C512, X28C513 memories that are frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3A illustrates the sequence of events on the bus. The software flow diagram in Figure 3B illustrates a method for polling the Toggle Bit.
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Software Data Protection
VCC 0V Data Addr CE tBLC MAX WE Byte or Page AAA 5555 55 2AAA A0 5555 Writes ok (VCC)
tWC
Write Protected
Note: All other timings and control pins are per page write timing requirements FIGURE 4A. TIMING SEQUENCE--SOFTWARE DATA PROTECT ENABLE SEQUENCE FOLLOWED BY BYTE OR PAGE WRITE
Software Algorithm
Write Data AA to Address 5555
Write Data 55 to Address 2AAA
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4A and 4B for the sequence. The three byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the X28C512, X28C513 will automatically disable further writes, unless another command is issued to cancel it. If no further commands are issued the X28C512, X28C513 will be write protected during power-down and after any subsequent power-up. The state of A15 while executing the algorithm is don't care. Note: Once initiated, the sequence of write operations should not be interrupted.
Optional Byte/Page Load Operation
Write Data 80 to Address 5555
Write Data XX to any Address
Write Last Byte to Last Address
After tWC Re-Enters Data Protected State
FIGURE 4B. WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION
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Resetting Software Data Protection
VCC
Data Addr CE
AAA 5555
55 2AAA
80 5555
AA 5555
55 2AAA
20 5555
tWC
Standard Operating Mode
WE
Note: All other timings and control pins are per page write timing requirements
FIGURE 5A. Reset Software Data Protection Timing Sequence
System Considerations
Write Data AA to Address 5555
Write Data 55 to Address 2AAA
Because the X28C512, X28C513 are frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is/are outputting data on the bus. Because the X28C512, X28C513 have two power modes, (standby and active), proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1F high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7F electrolytic bulk capacitor be placed between VCC and VSS for each 8 devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
Write Data A0 to Address 5555
Write Data AA to Address 5555
Write Data 55 to Address 2AAA
Write Data 20 to Address 5555
FIGURE 5B. SOFTWARE SEQUENCE TO DEACTIVATE SOFTWARE DATA PROTECTION
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28C512, X28C513 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted.
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Active Supply Current vs Ambient Temperature
14 VCC = 5V 13 ICC (mA) 12 50 11 10 9 8 -55 ICC (mA) 40 30 20 -10 +35 +80 +125 10 0 3 6 9 12 15 Frequency (MHz) Ambient Temperature (C) 60 -55C +25C +125C
ICC (RD) by Temperature Over Frequency
70 5.0 VCC
Standby Supply Current vs Ambient Temperature
0.24 0.22 0.2 ISB (mA) 0.18 0.16 0.14 0.12 0.1 -55 -10 +35 +80 +125 VCC = 5V
Ambient Temperature (C)
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Absolute Maximum Ratings
Temperature under bias X28C512, X28C513 . . . . . . . . . . . . . . . . . . . . . . . .-10C to +85C X28C512I/513I . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +135C X28C512M/513M . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on any pin with respect to VSS . . . . . . . . . . . . . . -1V to +7V D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300C
Recommended Operating Conditions
Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to +125C Supply Voltage Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V 10%
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Specifications
SYMBOL ICC ISB1 ISB2 ILI ILO VlL (Note 1) VIH (Note 1) VOL VOH NOTE:
Over recommended operating conditions, unless otherwise specified. TEST CONDITIONS CE = OE = VIL, WE = VIH, All I/O's = open, address inputs = 0.4V/2.4V Levels @ f = 5MHz CE = VIH, OE = VIL, All I/O's = open, other inputs = VIH CE = VCC - 0.3V, OE = VIL, All I/O's = Open, Other Inputs = VIH VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH -1 2 IOL = 2.1mA IOH = -400A 2.4 MIN MAX 50 3 500 10 10 0.8 VCC + 1 0.4 UNIT mA mA A A A V V V V
PARAMETER VCC current (active) (TTL inputs) VCC current (standby) (TTL inputs) VCC current (standby) (CMOS inputs) Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage
1. VIL min. and VIH max. are for reference only and are not tested.
Power-Up Timing
SYMBOL tPUR (Note 2) tPUW (Note 2) PARAMETER Power-up to read operation Power-up to write operation MAX 100 5 UNIT s ms
Capacitance
SYMBOL CI/O (Note 2) CIN (Note 2)
TA = +25C, f = 1MHz, VCC = 5V PARAMETER Input/output capacitance Input capacitance TEST CONDITIONS VI/O = 0V VIN = 0V MAX 10 10 UNIT pF pF
Endurance and Data Retention
PARAMETER Endurance Endurance Data retention NOTE: 2. This parameter is periodically sampled and not 100% tested. MIN 10,000 100,000 100 MAX UNIT Cycles per byte Cycles per page Years
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A.C. Conditions of Test
Input pulse levels Input rise and fall times Input and output timing levels 0V to 3V 10ns 1.5V
Output 5V
Equivalent A.C. Load Circuit
1.92k
Mode Selection
CE OE WE MODE Read Write Standby and write inhibit Write inhibit Write inhibit I/O DOUT DIN High Z -- -- POWER Active Active Standby -- --
1.37K
100pF
L L H X X
L H X L X
H L X X H
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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AC Electrical Specifications
Over the recommended operating conditions, unless otherwise specified. X28C512-90 X28C513-90 SYMBOL READ CYCLE LIMITS tRC tCE tAA tOE tLZ (Note 3) tOLZ (Note 3) tHZ (Note 3) tOHZ (Note 3) tOH Read cycle time Chip enable access time Address access time Output enable access time CE LOW to active output OE LOW to active output CE HIGH to high Z output OE HIGH to high Z output Output hold from address change 0 0 0 40 40 0 90 90 90 40 0 0 50 50 0 120 120 120 50 0 0 50 50 0 150 150 150 50 0 0 50 50 0 200 200 200 50 0 0 50 50 250 250 250 50 ns ns ns ns ns ns ns ns ns PARAMETER MIN MAX X28C512-12 X28C513-12 MIN MAX X28C512-15 X28C513-15 MIN MAX X28C512-20 X28C513-20 MIN MAX X28C512-25 X28C513-25 MIN MAX UNIT
Read Cycle
tRC Address tCE CE tOE OE VIH WE tOLZ tLZ HIGH Z Data I/O Data Valid tAA Data Valid tOH tHZ tOHZ
NOTE: 3. tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
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Write Cycle Limits
SYMBOL tWC (Note 4) tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV tDS tDH tDW tBLC Write cycle time Address setup time Address hold time Write setup time Write hold time CE pulse width OE HIGH setup time OE HIGH hold time WE pulse width WE High recovery Data valid Data setup Data hold Delay to next write Byte load cycle 50 0 10 0.2 100 0 50 0 0 100 10 10 100 100 1 PARAMETER MIN MAX 10 UNIT ms ns ns ns ns ns ns ns ns ns s ns ns s s
WE Controlled Write Cycle
tWC Address tAS tCS CE tAH tCH
OE tOES tWP WE tDV Data In tDS HIGH Z Data Out Data Valid tDH tOEH
NOTE: 4. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete the internal write operation.
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CE Controlled Write Cycle
tWC Address tAS CE tOES OE tOEH tCS WE tDV Data In tDS HIGH Z Data Out Data Valid tDH tCH tWPH tAH tCW
Page Write Cycle
OE
(Note 5)
CE tWP WE tWPH tBLC
Address*
(Note 6)
I/O Byte 0 Byte 1 Byte 2 Byte n Byte n+1
Last Byte Byte n+2 tWC *For each successive write within the page write operation, A7-A15 should be the same or writes to an unknown address could occur.
NOTES: 5. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 6. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
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DATA Polling Timing Diagram (Note 7)
Address An An An
CE
WE tOEH tOES
OE tDW I/O7 DIN = X DOUT = X tWC DOUT = X
Toggle Bit Timing Diagram
CE
WE tOEH OE tDW HIGH Z I/O6 * tWC * tOES
*Starting and ending state will vary, depending upon actual tWC.
NOTE: 7. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
17
FN8106.1 September 29, 2005
X28C512, X28C513 Packaging Information
32-Lead Hermetic Dual In-Line Package Type D
1.690 (42.95) Max.
0.610 (15.49) 0.500 (12.70)
Pin 1 0.005 (0.13) Min. 0.100 (2.54) Max.
Seating Plane 0.232 (5.90) Max. 0.060 (1.52) 0.015 (0.38)
0.150 (3.81) Min.
0.200 (5.08) 0.125 (3.18)
0.110 (2.79) 0.090 (2.29) Typ. 0.100 (2.54)
0.065 (1.65) 0.033 (0.84) Typ. 0.055 (1.40)
0.023 (0.58) 0.014 (0.36) Typ. 0.018 (0.46)
0.620 (15.75) 0.590 (14.99) Typ. 0.614 (15.60)
0.015 (0.38) 0.008 (0.20)
0 15
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
FN8106.1 September 29, 2005
X28C512, X28C513 Packaging Information
32-Pad Ceramic Leadless Chip Carrier Package Type E
0.300 (7.62) BSC 0.150 (3.81) BSC 0.015 (0.38) 0.003 (0.08) 0.020 (0.51) x 45 Ref.
0.095 (2.41) Pin 1 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.200 (5.08) BSC 0.015 (0.38) Min. 0.028 (0.71) 0.022 (0.56) (32) Plcs. 0.050 (1.27) BSC DIA.
0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS.
0.040 (1.02) x 45 Ref. Typ. (3) Plcs.
0.458 (11.63) 0.442 (11.22) 0.458 (11.63) -0.120 (3.05) 0.060 (1.52)
0.088 (2.24) 0.050 (1.27)
0.560 (14.22) 0.540 (13.71)
0.558 (14.17) --
0.400 (10.16) BSC
Pin 1 Index Corner
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: 1% NLT 0.005 (0.127)
19
FN8106.1 September 29, 2005
X28C512, X28C513 Packaging Information
32-Lead Ceramic Flat Pack Type F
1.228 (31.19) 1.000 (25.40) Pin 1 Index 1 32
0.019 (0.48) 0.015 (0.38)
0.050 (1.27) BSC 0.830 (21.08) Max.
0.045 (1.14) Max. 0.005 (0.13) Min.
0.007 (0.18) 0.004 (0.10)
0.440 (11.18) 0.430 (10.93)
0.120 (3.05) 0.090 (2.29)
0.370 (9.40) 0.270 (6.86) 0.347 (8.82) 0.330 (8.38) 0.030 (0.76) Min. 0.026 (0.66) Min.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
FN8106.1 September 29, 2005
X28C512, X28C513 Packaging Information
32-Lead Plastic Leaded Chip Carrier Package Type J
0.420 (10.67)
0.050" Typical
0.030" Typical 32 Places
0.510" Typical 0.400" 0.050 (1.27) Typ.
0.050" Typical
FOOTPRINT
0.300" Ref. 0.410"
0.021 (0.53) 0.045 (1.14) x 45 0.013 (0.33) Typ. 0.017 (0.43) Seating Plane 0.004 Lead CO - Planarity -- 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) Typ. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07)
0.495 (12.57) 0.485 (12.32) Typ. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) Typ. 0.450 (11.43) 0.300 (7.62) Ref. Pin 1
0.595 (15.11) 0.585 (14.86) Typ. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) Typ. 0.550 (13.97) 0.400 (10.16)Ref. 3 Typ.
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
21
FN8106.1 September 29, 2005
X28C512, X28C513 Packaging Information
32-Lead Plastic Dual In-Line Package Type P
1.665 (42.29) 1.644 (41.76)
0.557 (14.15) 0.510 (12.95) Pin 1 Index Pin 1 1.500 (38.10) Ref. 0.085 (2.16) 0.040 (1.02)
Seating Plane 0.160 (4.06) 0.125 (3.17)
0.160 (4.06) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38)
0.110 (2.79) 0.090 (2.29)
0.070 (17.78) 0.030 (7.62)
0.022 (0.56) 0.014 (0.36)
0.625 (15.88) 0.590 (14.99)
Typ. 0.010 (0.25)
0 15
NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
22
FN8106.1 September 29, 2005
X28C512, X28C513 Packaging Information
32-Lead Ceramic Small Outline Gull Wing Package Type R
0.060 Nom.
See Detail "A" For Lead Information 0.340 0.007 0.165 Typ.
0.020 Min. 0.015 R Typ.
0.035 Typ.
0.015 R Typ. Detail "A"
0.035 Min.
0.019 0.015
0.050" Typical
0.050" Typical 0.830 Max. 0.750 0.005 0.560" Typical
0.050
FOOTPRINT
0.030" Typical 32 Places
0.440 Max. 0.560 Nom.
NOTES: 1. ALL DIMENSIONS IN INCHES 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
23
FN8106.1 September 29, 2005
X28C512, X28C513 Packaging Information
36-Lead Ceramic Pin Grid Array Package Type K
15 13 12 10 8 6 Typ. 0.180 (.010) (4.57 .25) 4 Corners 14 11 9 7 5 4
17 16
19 18
21 20
22 A 0.008 (0.20) 23 25 27 29 24 26 A 28 30 Typ. 0.100 (2.54) All Leads 31 0.050 (1.27)
NOTE: Leads 5, 14, 23, & 32
2 3
36 1
34 35
32 33
Typ. 0.180 (.010) (4.57 .25) 4 Corners Pin 1 Index
0.120 (3.05) 0.100 (2.54) 0.072 (1.83) 0.062 (1.57)
0.770 (19.56) 0.750 (19.05) SQ A A 0.020 (0.51) 0.016 (0.41)
0.185 (4.70) 0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
24
FN8106.1 September 29, 2005
X28C512, X28C513 Packaging Information
40-Lead Thin Small Outline Package (TSOP) Type T
0.493 (12.522) 0.483 (12.268) 0.045 (1.143) 0.035 (0.889) Pin #1 Ident O 0.040 (1.016) 0.005 (0.127) Dp. O 0.030 (0.762) X 0.003 (0.076) Dp. 1 0.0197 (0.500)
(0.038) 0.965
0.048 (1.219)
0.396 (10.058) 0.392 (9.957) 0.007 (0.178) 15 Typ. Seating Plane 0.010 (0.254) 0.006 (0.152) 0.040 (1.016) Detail A 0.032 (0.813) Typ.
A 0.0025 (0.065) Seating Plane 0.557 (14.148) 0.547 (13.894) 0.006 (0.152) Typ. 4 Typ.
0.017 (0.432) 0.017 (0.432) 0.020 (0.508) Typ.
14.80 0.05 (0.583 0.002) 0.30 0.05 Solder Pads
(0.012 0.002)
Typical 40 Places 15 Eq. Spc.@ 0.50 0.04 0.0197 0.016 = 9.50 0.06 (0.374 0.0024) Overall Tol. Non-Cumulative
FOOTPRINT
0.17 (0.007) 0.03 (0.001) 1.30 0.05 (0.051 0.002)
0.50 0.04 (0.0197 0.0016)
NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 25
FN8106.1 September 29, 2005

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